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2SK1764
Silicon N Channel MOS FET
Application
Low frequency amplifier High speed switching
UPAK
3
2
1
Features
* Low on-resistance * High speed switching * 4 V Gate drive device can be driven from 5 V source * Suitable for switchingregulator, DC-DC converter
2, 4 1
4
1. 1. Gate Gate 2. Drain 2. Drain 3. Source 3. Source 4. Drain 4. Drain
3
Table 1 Absolute Maximum Ratings (Ta = 25C)
Item Drain to source voltage Gate to source voltage Drain current Drain peak current Channel power dissipation Channel temperature Storage temperature * ** *** Symbol VDSS VGSS ID ID(pulse)* Pch** Tch Tstg Ratings 60 20 2 4 1 150 -55 to +150 Unit V V A A W C C
-------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------
PW 100 s, duty cycle 10 % Value on the alumina ceramic board (12.5 x 20 x 0.7 mm) Marking is "KY".
2SK1764
Table 2 Electrical Characteristics (Ta = 25C)
Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source cutoff voltage Drain to source cutoff current Gate to source cutoff current Static drain to source on state resistance Static drain to source on state resistance Forward transfer admittance Symbol V(BR)DSS V(BR)GSS VGS(off) IDSS IGSS RDS(on)1 RDS(on)2 |yfs| Ciss Coss Crss ton toff Min 60 Typ -- Max -- Unit V Test Conditions ID = 10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = 10 V, ID = 1 mA VDS = 50 V, VGS = 0 VGS = 15 V, VDS = 0 VGS = 10 V ID = 1 A* VGS = 4 V ID = 1 A* VDS = 10 V ID = 1 A* VDS = 10 V VGS = 0 f = 1 MHz VDS = 10 V, ID = 1 A* RL = 30
-------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------
20 -- -- V
--------------------------------------------------------------------------------------
1 -- -- -- -- -- -- 0.3 2 10 5 0.45 V A A
-------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------
-- 0.4 0.60
--------------------------------------------------------------------------------------
0.9 1.7 -- S
--------------------------------------------------------------------------------------
Input capacitance Output capacitance Reverse transfer capacitance Turn on time Turn off time * Pulse Test -- -- -- -- -- 140 75 20 18 80 -- -- -- -- -- pF pF pF ns ns
---------------------------------------------------------------- ---------------------------------------------------------------- -------------------------------------------------------------------------------------- ----------------------------------------------------------------
--------------------------------------------------------------------------------------
2SK1764
Maximum Channel Power Dissipation Curve
1.6 10
Safe Operation Area
Channel Power Dissipation Pch** (W) (** on the almina ceramic board)
3
PW
1m
ID (A)
1.2
s
= 10
1.0
) in on n S( tio is ra ea R D y pe r O is a d b th ite lim
s m (1
Drain Current
D
o sh
C
0.8
0.3
op
t)
er
at
io
n
0.1
0.4 0.03 Ta = 25C 0 50 100 Ambient Temperature 150 Ta (C) 200 0.01 0.1 0.3 1.0 3 10 V DS 30 (V) 100
Drain to Source Voltage
Typical Output Characteristics
5 10V 7V 5V 4.5V Pulse Test 4V 4 I D (A) 5
Typical Transfer Characteristics
VDS = 10V Pulse Test
4 I D (A)
3
3.5V
3
Drain Current
2 3V
Drain Current
2
1
V GS = 2.5V
1 75C -25C Ta = 25 C
0
6 8 4 Drain to Source Voltage V DS (V)
2
10
0
1
2
3
4 V GS (V)
5
Gate to Source Voltage
2SK1764
Drain to Source Saturation Voltage vs. Gate to Source Voltage
(V) 1.0 Pulse Test Static Drain to Source On State Resistance R DS (on) ( ) 5
Static Drain to Source On State Resistance vs. Drain Current
Drain to Source Saturation Voltage V DS (on)
Pulse Test 2 VGS = 4V 1.0
0.8 2A 0.6
0.5
0.4
1A I D = 0.5A
10V 0.2
0.2
0.1
0
6 4 Gate to Source Voltage
2
8 V GS (V)
10
0.05 0.05
0.1
0.2
0.5
1.0
2
5
Drain Current I D (A)
Static Drain to Source On State Resistance vs. Case Temperature
1.0 Pulse Test Static Drain to Source On State Resistance R DS (on) ( ) Forward Transfer Admittance |yfs| (S) 5
Forward Transfer Admittance vs. Drain Current
V DS = 10V Pulse Test Ta = 25C
0.8 I D = 2A 1A 0.5A V GS = 4V 0.4 2A 0.2 V GS = 10V 0.5A 1A
2
1.0
0.6
0.5
0.2
0.1 0.05 0.05
0 -40
0
40
80
120
160
0.1
0.2
0.5
1.0
2
5
Case Temperature Tc (C)
Drain Current ID (A)
2SK1764
Typical Capacitance vs. Drain to Source Voltage
1000 V GS = 0 f = 1 MHz 300 C (pF) Ciss 100 Coss 30 Crss 10 Switching Time t (ns) 100
Switching Time vs. Drain Current
t d (off) 50 tf 20 ton
Capacitance
10 V GS = 10V PW = 2s, duty < 1% 5
3
2
1 0 10 20 30 40 Drain to Source Voltage V DS (V) 50
1 0.05
0.1
0.2
0.5
1.0
2
5
Drain Current I D (A)
Reverse Drain Current vs. Source to Drain Voltage
5 Pulse Test 4
Reverse Drain Current I DR (A)
3
5V 2
VGS = 0
1
0
1.2 1.6 0.4 0.8 Source to Drain Voltage VSD (V)
2.0

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